This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
In conventional circuit designs, memory sub-systems are typically restricted by various load constraints. These memory sub-systems typically utilize conventional clock driver topology that are substantially sized due to a large load that they drive to generate a global timing pulse (GTP) and further due to a cascading effect that the large load has on a slew rate of various derived clocks used for memory operations. Thus, there exists a need to improve clock driver topology that could be used to reduce this loading effect and also reduce area in double-pumped memories.